A Sub-50-fs RMS Jitter, 103.5-GHz Fundamental-Sampling PLL With an Extended Loop Bandwidth-Reference-Cited by-同舟云学术

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A Sub-50-fs RMS Jitter, 103.5-GHz Fundamental-Sampling PLL With an Extended Loop Bandwidth

Published:2023 Issue: Volume:6 Page:201-204
ISSN:2573-9603
Container-title:IEEE Solid-State Circuits Letters
language:
Short-container-title:IEEE Solid-State Circuits Lett.

Author:

Bang Jooeun¹^ORCID,Jung Seohee¹^ORCID,Kim Jaeho¹^ORCID,Park Suneui²^ORCID,Choi Jaehyouk³^ORCID

Affiliation:

1. School of Electrical Engineering, Korea Advanced Institute of Science and Technology, Daejeon, South Korea

2. Department of Memory Division, Samsung Electronics, Hwaseong, South Korea

3. Department of Electrical and Computer Engineering, Seoul National University, Seoul, South Korea

Funder

National Research and Development Program through the National Research Foundation of Korea

Institute of Information and Communications Technology Planning and Evaluation

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering

Link

http://xplorestaging.ieee.org/ielx7/8011414/10016898/10185597.pdf?arnumber=10185597

Reference8 articles.

1. Phase Noise Analysis of Periodically ON/OFF Switched Oscillators

2. A multiple-crystal interface PLL with VCO realignment to reduce phase noise

3. An Ultra-Low Jitter, Low-Power, 102-GHz PLL Using a Power-Gating Injection-Locked Frequency Multiplier-Based Phase Detector

4. A 300GHz 52mW CMOS Receiver with On-Chip LO Generation

5. A 28-nm 75-fsrms Analog Fractional-$N$ Sampling PLL With a Highly Linear DTC Incorporating Background DTC Gain Calibration and Reference Clock Duty Cycle Correction

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