A 40 nm 512 kb Cross-Point 8 T Pipeline SRAM With Binary Word-Line Boosting Control, Ripple Bit-Line and Adaptive Data-Aware Write-Assist-Reference-Cited by-同舟云学术

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A 40 nm 512 kb Cross-Point 8 T Pipeline SRAM With Binary Word-Line Boosting Control, Ripple Bit-Line and Adaptive Data-Aware Write-Assist

Published:2014-12 Issue:12 Volume:61 Page:3416-3425
ISSN:1549-8328
Container-title:IEEE Transactions on Circuits and Systems I: Regular Papers
language:
Short-container-title:IEEE Trans. Circuits Syst. I

Author:

Lien Nan-Chun,Chu Li-Wei,Chen Chien-Hen,Yang Hao-I.,Tu Ming-Hsien,Kan Paul-Sen,Hu Yong-Jyun,Chuang Ching-Te,Jou Shyh-Jye,Hwang Wei

Funder

Ministry of Economic Affairs in Taiwan

National Science Council Taiwan

Ministry of Education in Taiwan under ATU Program

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering

Link

http://xplorestaging.ieee.org/ielx7/8919/6964837/06891326.pdf?arnumber=6891326

Cited by 31 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. A Single Bitline Highly Stable, Low Power With High Speed Half-Select Disturb Free 11T SRAM Cell;ACM Transactions on Design Automation of Electronic Systems;2024-07-09

2. Energy-Efficient Single-Ended Read/Write 10T Near-Threshold SRAM;IEEE Transactions on Circuits and Systems I: Regular Papers;2023-05

3. A 128-kbit GC-eDRAM With Negative Boosted Bootstrap Driver for 11.3× Lower-Refresh Frequency at a 2.5% Area Overhead in 28-nm FD-SOI;IEEE Solid-State Circuits Letters;2023

4. Review of Approximate Computing in Image Processing Applications;2022 4th International Conference on Artificial Intelligence and Speech Technology (AIST);2022-12-09

5. A bit-interleaving 12T bitcell with built-in write-assist for sub-threshold SRAM;IEICE Electronics Express;2022-05-25

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