Comparator Power Minimization Analysis for SAR ADC Using Multiple Comparators-Reference-Cited by-同舟云学术

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Comparator Power Minimization Analysis for SAR ADC Using Multiple Comparators

Published:2015-10 Issue:10 Volume:62 Page:2369-2379
ISSN:1549-8328
Container-title:IEEE Transactions on Circuits and Systems I: Regular Papers
language:
Short-container-title:IEEE Trans. Circuits Syst. I

Author:

Ahmadi Muhammad,Namgoong Won

Funder

National Science Foundation

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering

Link

http://xplorestaging.ieee.org/ielx7/8919/7277125/07244259.pdf?arnumber=7244259

Cited by 23 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. A Reconfigurable 12-to-18-Bit Dynamic Zoom ADC With Pole-Optimized Technique;IEEE Transactions on Circuits and Systems I: Regular Papers;2023-05

2. A 16-bit 300-kS/s foreground calibration SAR ADC with single-ended/differential configurable input modes;Microelectronics Journal;2022-10

3. Low-Power SAR ADC Design: Overview and Survey of State-of-the-Art Techniques;IEEE Transactions on Circuits and Systems I: Regular Papers;2022-06

4. Concurrent Effect of Redundancy and Switching Algorithms in SAR ADCs;2022 IEEE International Symposium on Circuits and Systems (ISCAS);2022-05-28

5. Design of High Speed 8-Bit Magnitude Comparator for Security Application;2022 IEEE International Conference on Distributed Computing and Electrical Circuits and Electronics (ICDCECE);2022-04-23

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