Concurrent Effect of Redundancy and Switching Algorithms in SAR ADCs-Reference-Cited by-同舟云学术

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Concurrent Effect of Redundancy and Switching Algorithms in SAR ADCs

Published:2022-05-28 Issue: Volume: Page:
ISSN:
Container-title:2022 IEEE International Symposium on Circuits and Systems (ISCAS)
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Author:

Ricci Luca¹,Scaletti Lorenzo¹,Be Gabriele¹,Bertulessi Luca¹,Levantino Salvatore¹,Samori Carlo¹,Bonfanti Andrea¹

Affiliation:

1. Politecnico di Milano,Dipartimento di elettronica, informazione e bioingegneria (DEIB),Milan,Italy

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/9937201/9937203/09937809.pdf?arnumber=9937809

Reference29 articles.

1. A 12-bit 104 MS/s SAR ADC in 28 nm CMOS for Digitally-Assisted Wireless Transmitters

2. A 7b 2.6mW 900MS/s Nonbinary 2-then-3b/cycle SAR ADC with Background Offset Calibration

3. A Compact 8-bit, 8 GS/s 8×TI SAR ADC in 16nm with 45dB SNDR and 5 GHz ERBW

4. A 12b 50MS/s 2.1mW SAR ADC with redundancy and digital background calibration

5. Low-power high-performance sar adc with redundancy and digital background calibration;chang,2009

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