A Reconfigurable 12-to-18-Bit Dynamic Zoom ADC With Pole-Optimized Technique
Author:
Affiliation:
1. Shaanxi Key Laboratory of Integrated Circuits and Systems, School of Microelectronics, Xidian University, Xi’an, China
Funder
National Natural Science Foundation of China
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
Subject
Electrical and Electronic Engineering,Hardware and Architecture
Link
http://xplorestaging.ieee.org/ielx7/8919/10109891/10067243.pdf?arnumber=10067243
Reference35 articles.
1. A 440-μW, 109.8-dB DR, 106.5-dB SNDR Discrete-Time Zoom ADC With a 20-kHz BW
2. A high DR multi-channel stage-shared hybrid front-end for integrated power electronics controller
3. A Dynamic Zoom ADC With 109-dB DR for Audio Applications
4. Design of High-Resolution Continuous-Time Delta–Sigma Data Converters With Dual Return-to-Open DACs
5. A High Area-Efficiency 14-bit SAR ADC With Hybrid Capacitor DAC for Array Sensors
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