A 13-ENOB, 5 MHz BW, 3.16 mW multi-bit continuous-time ΔΣ ADC in 28 nm CMOS with excess-loop-delay compensation embedded in SAR quantizer

Author:

Wei Guowen,Shettigar Pradeep,Su Feng,Yu Xinyu,Kwan Tom

Publisher

IEEE

Cited by 6 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献

1. A 2MHz-BW 96.8dB-SNDR 98dB-SNR CT-Zoom ADC With Residue Feedforward, Redundancy and Fully LMS-Based Calibration;ESSCIRC 2023- IEEE 49th European Solid State Circuits Conference (ESSCIRC);2023-09-11

2. A Highly Multi-Bit Continuous-Time Delta-Sigma Modulator ADC with 9-Bit Feedback;2023 IEEE 66th International Midwest Symposium on Circuits and Systems (MWSCAS);2023-08-06

3. Bitwise ELD Compensation in Δ∑ Modulators;2022 IEEE International Symposium on Circuits and Systems (ISCAS);2022-05-28

4. A 3.7-mW 12.5-MHz 81-dB SNDR 4th-Order Continuous-Time DSM With Single-OTA and 2nd-Order Noise-Shaping SAR;IEEE Open Journal of the Solid-State Circuits Society;2022

5. Continuous-Time ADCs for Automotive Applications;Next-Generation ADCs, High-Performance Power Management, and Technology Considerations for Advanced Integrated Circuits;2019-10-25

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