Bitwise ELD Compensation in Δ∑ Modulators-Reference-Cited by-同舟云学术

Bitwise ELD Compensation in Δ∑ Modulators

Published:2022-05-28 Issue: Volume: Page:
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Container-title:2022 IEEE International Symposium on Circuits and Systems (ISCAS)
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Author:

Pietzko Michael¹,Ungethum Jonathan¹,Kauffman John G.¹,Li Qiang²,Ortmanns Maurits¹

Affiliation:

1. Institute of Microelectronics, University of Ulm,Ulm,Germany

2. Institute of Integrated Circuits and Systems, University of Electronic Science and Technology of China,Chengdu,China

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/9937201/9937203/09937305.pdf?arnumber=9937305

Reference14 articles.

1. Continuous-Time Sigma-Delta A/D Conversion: Fundamentals, Performance Limits, and Robust Implementations, ser. Springer Series in Advanced Microelectronics;ortmanns,2006

2. A Comparative Study on Excess-Loop-Delay Compensation Techniques for Continuous-Time Sigma–Delta Modulators

3. Influence of Excess Loop Delay on the STF of Continuous-Time Delta-Sigma Modulators

4. A 13-ENOB, 5 MHz BW, 3.16 mW multi-bit continuous-time ΔΣ ADC in 28 nm CMOS with excess-loop-delay compensation embedded in SAR quantizer

5. A 7.2 mW 75.3 dB SNDR 10 MHz BW CT Delta-Sigma Modulator Using Gm-C-Based Noise-Shaped Quantizer and Digital Integrator

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