Delay Error Shaping in ΔΣ Modulators Using Time-Interleaved High Resolution Quantizers
Author:
Affiliation:
1. Institute of Microelectronics, University of Ulm, Ulm, Germany
Funder
German Research Foundation-DFG
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
Subject
Electrical and Electronic Engineering,Hardware and Architecture
Link
http://xplorestaging.ieee.org/ielx7/8919/10164683/10122669.pdf?arnumber=10122669
Reference24 articles.
1. A Hybrid-Loop Structure and Interleaved Noise-Shaped Quantizer for a Robust 100-MHz BW and 69-dB DR DSM
2. A 930 mW 69 dB-DR 465 MHz-BW CT 1–2 MASH ADC in 28 nm CMOS;dong;IEEE Int Solid-State Circuits Conf (ISSCC) Dig Tech Papers,2016
3. A Continuous-Time $\Delta \Sigma$ ADC Utilizing Time Information for Two Cycles of Excess Loop Delay Compensation
4. Explicit analysis of channel mismatch effects in time-interleaved ADC systems
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1. A Reconfigurable Continuous-Time Delta-Sigma Modulator Structure Using Hybrid Loop Filter and Time-Interleaved Quantizer;2024 IEEE International Symposium on Circuits and Systems (ISCAS);2024-05-19
2. A Two-Channel Time-Interleaved Continuous-Time Third-Order CIFF-Based Delta-Sigma Modulator;IEEE Transactions on Circuits and Systems I: Regular Papers;2023-12
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