A 3.7-mW 12.5-MHz 81-dB SNDR 4th-Order Continuous-Time DSM With Single-OTA and 2nd-Order Noise-Shaping SAR

Author:

Shi Wei1ORCID,Liu Jiaxin2ORCID,Mukherjee Abhishek1ORCID,Yang Xiangxing1ORCID,Tang Xiyuan3ORCID,Shen Linxiao4ORCID,Zhao Wenda1ORCID,Sun Nan1

Affiliation:

1. Department of Electrical and Computer Engineering, The University of Texas at Austin, Austin, TX, USA

2. Institute of Integrated Circuits and Systems, University of Electronic Science and Technology of China, Chengdu, China

3. Institute for Artificial Intelligence and School of Integrated Circuit, Peking University, Beijing, China

4. School of Integrated Circuit, Peking University, Beijing, China

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Reference43 articles.

1. 20.4 An 8 × - OSR 25MHz-BW 79.4dB/74dB DR/SNDR CT Δ σ Modulator Using 7b Linearized Segmented DACs with Digital Noise-Coupling-Compensation Filter in 7nm FinFET CMOS

2. A 28fJ/conv-step CT ?? modulator with 78dB DR and 18MHz BW in 28nm CMOS using a highly digital multibit quantizer;shu;IEEE Int Solid-State Circuits Conf Dig Tech Papers,2013

3. A low-noise self-calibrating dynamic comparator for high-speed ADCs

4. A X-coupled differential single-opamp resonator for low power continuous time ??-ADCs;zeller;Proc Ph D Res Microelectron Electron Conf,2011

5. 20.2 A 40MHz-BW 320MS/s Passive Noise-Shaping SAR ADC With Passive Signal-Residue Summation in 14nm FinFET

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