An Efficient Architecture for Signed Carry Save Multiplication-Reference-Cited by-同舟云学术

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An Efficient Architecture for Signed Carry Save Multiplication

Published:2020-01-01 Issue:1 Volume:3 Page:9-12
ISSN:2573-9689
Container-title:IEEE Letters of the Computer Society
language:
Short-container-title:IEEE Lett. of the Comput. Soc.

Author:

Patali Pramod^ORCID,Kassim Shahana Thottathikkulam

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

General Earth and Planetary Sciences,General Engineering,General Environmental Science

Link

http://xplorestaging.ieee.org/ielx7/8012254/8950490/08979361.pdf?arnumber=8979361

Cited by 8 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. An Efficient Multiplier Architecture using Improved Full Adder Circuit;2024 IEEE International Students' Conference on Electrical, Electronics and Computer Science (SCEECS);2024-02-24

2. Area and Energy Efficient Booth Radix-4 Signed Multiplier Using Verilog;Lecture Notes in Networks and Systems;2024

3. Exact and approximate multiplications for signal processing applications;Microelectronics Journal;2023-02

4. Analysis of Delay in 16 × 16 Signed Binary Multiplier;Proceedings of the International Conference on Paradigms of Computing, Communication and Data Sciences;2023

5. Design of Low Power Modular (x mod p) Reduction Unit Based on Switching Activity for Data Security Applications;Lecture Notes in Electrical Engineering;2022-12-01

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