An Efficient Multiplier Architecture using Improved Full Adder Circuit-Reference-Cited by-同舟云学术

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An Efficient Multiplier Architecture using Improved Full Adder Circuit

Published:2024-02-24 Issue: Volume:10 Page:1-4
ISSN:
Container-title:2024 IEEE International Students' Conference on Electrical, Electronics and Computer Science (SCEECS)
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Author:

Sasmal Rahul¹,Singh Abhay Pratap¹,Baghel R.K¹,Rajput Vishal¹

Affiliation:

1. Maulana Azad National Institute of Techonology,Department of Electronics and Communication Engineering,Bhopal,India

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/10481805/10481679/10482301.pdf?arnumber=10482301

Reference13 articles.

1. A Reduced Complexity Wallace Multiplier Reduction

2. Low-Cost and High-Performance 8 × 8 Booth Multiplier

3. High throughput FIR filter architectures using retiming and modified CSLA based adders

4. Enhanced low dimensional MOSFETs with variation of high K dielectric materials

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