Low-Cost and High-Performance 8 × 8 Booth Multiplier
Author:
Publisher
Springer Science and Business Media LLC
Subject
Applied Mathematics,Signal Processing
Link
http://link.springer.com/article/10.1007/s00034-019-01044-x/fulltext.html
Reference13 articles.
1. V.B.P. Biradar, G. Vishwas, C.S. Chetan, Design and performance analysis of modified unsigned braun and signed Baugh–Wooley multiplier, in International Conference on Electrical, Electronics, Communication, Computer, and Optimization Techniques (2017). https://doi.org/10.1109/iceeccot.20178284612
2. N.V.V.K. Boppana, S. Ren, A low-power and area-efficient 64-bit digital comparator. Circuits Syst. Comput. 25(12), 1650148–1650163 (2016)
3. A.R. Cooper, Parallel architecture modified Booth multiplier. IEE Proc. G Electron. Circuits Syst. 135(3), 125–128 (1988)
4. G. Divya, A. Amonkar, Design and implementation of high speed modified Booth multiplier using hybrid adder. Comput. Methodol. Commun. (2017). https://doi.org/10.1109/ICCMC.2017.8282661
5. F. Elguibaly, A fast parallel multiplier—accumulator using the modified Booth algorithm. IEEE Trans. Circuits Syst. 47(9), 902–908 (2000)
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