Publisher
Institute of Electrical and Electronics Engineers (IEEE)
Cited by
5 articles.
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1. Towards Reliability Assessment of Systolic Arrays against Stuck-at Faults;2023 53rd Annual IEEE/IFIP International Conference on Dependable Systems and Networks - Supplemental Volume (DSN-S);2023-06
2. An Online and Real-Time Fault Detection and Localization Mechanism for Network-on-Chip Architectures;ACM Transactions on Architecture and Code Optimization;2016-06-27
3. Determination of combinational logic circuit reliability through generation of fault diagnosis tests;Microelectronics Reliability;1988-01
4. Literaturverzeichnis;Fehlerdiagnose für Schaltnetze aus Modulen mit partiell injektiven Pfadfunktionen;1987
5. High-Speed Logic Level Fault Simulation;Design and Test Technology for Dependable Systems-on-Chip