An Online and Real-Time Fault Detection and Localization Mechanism for Network-on-Chip Architectures

Author:

Chrysanthou Kypros1,Englezakis Panayiotis1,Prodromou Andreas1,Panteli Andreas1,Nicopoulos Chrysostomos1,Sazeides Yiannakis1,Dimitrakopoulos Giorgos2

Affiliation:

1. University of Cyprus, Nicosia, Cyprus

2. Democritus University of Thrace, Xanthi, Greece

Abstract

Networks-on-Chip (NoC) are becoming increasingly susceptible to emerging reliability threats. The need to detect and localize the occurrence of faults at runtime is steadily becoming imperative. In this work, we propose NoCAlert , a comprehensive online and real-time fault detection and localization mechanism that demonstrates 0% false negatives within the interconnect for the fault models and stimulus set used in this study. Based on the concept of invariance checking, NoCAlert employs a group of lightweight microchecker modules that collectively implement real-time hardware assertions. The checkers operate concurrently with normal NoC operation, thus eliminating the need for periodic, or triggered-based, self-testing. Based on the pattern/signature of asserted checkers, NoCAlert can pinpoint the location of the fault at various granularity levels. Most important, 97% of the transient and 90% of the permanent faults are detected instantaneously, within a single clock cycle upon fault manifestation. The fault localization accuracy ranges from 90% to 100%, depending on the desired localization granularity. Extensive cycle-accurate simulations in a 64-node CMP and analysis at the RTL netlist-level demonstrate the efficacy of the proposed technique.

Funder

Harpa, Project

European Commission 7th RTD Framework Program - Information and Communication Technologies: Computing Systems

Publisher

Association for Computing Machinery (ACM)

Subject

Hardware and Architecture,Information Systems,Software

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1. Sixer: A low-overhead, fully-distributed test scheme with guaranteed delivery of packets in networks-on-chip;Microelectronics Reliability;2023-03

2. A new architecture for online error detection and isolation in network on chip;Journal of High Speed Networks;2020-12-23

3. On hardware-trojan-assisted power budgeting system attack targeting many core systems;Journal of Systems Architecture;2020-10

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5. Monitor and Knob Techniques in Network-on-Chip Architectures;Harnessing Performance Variability in Embedded and High-performance Many/Multi-core Platforms;2018-10-24

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