Yield Maximization of Flip-Flop Circuits Based on Deep Neural Network and Polyhedral Estimation of Nonlinear Constraints-Reference-Cited by-同舟云学术

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Yield Maximization of Flip-Flop Circuits Based on Deep Neural Network and Polyhedral Estimation of Nonlinear Constraints

Published:2024 Issue: Volume:12 Page:113944-113959
ISSN:2169-3536
Container-title:IEEE Access
language:
Short-container-title:IEEE Access

Author:

Sajjadi Sayed Alireza¹^ORCID,Sadrossadat Sayed Alireza²^ORCID,Moftakharzadeh Ali¹^ORCID,Nabavi Morteza³^ORCID,Sawan Mohamad⁴^ORCID

Affiliation:

1. Department of Electrical Engineering, Yazd University, Yazd, Iran

2. Department of Computer Engineering, Yazd University, Yazd, Iran

3. Department of Electrical and Computer Engineering, Polytechnique Montréal, Montreal, QC, Canada

4. Center of Excellence in Biomedical Research on Advances-on-Chips Neurotechnologies (CenBRAIN Neurotech), School of Engineering, Westlake University, Hangzhou, Zhejiang, China

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Link

http://xplorestaging.ieee.org/ielx8/6287639/10380310/10636168.pdf?arnumber=10636168

Reference43 articles.

1. A Statistical Gate Sizing Method for Timing Yield and Lifetime Reliability Optimization of Integrated Circuits

2. Analog Circuit Yield Optimization via Freeze–Thaw Bayesian Optimization Technique

3. Reliable Circuit Design Using a Fast Incremental-Based Gate Sizing Under Process Variation

4. A Yield Prediction Method Based on Nonparametric Statistical and Comparison With a Networks Method

5. Accurate and Insightful Closed-Form Prediction of Subthreshold SRAM Hold Failure Rate

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