Accurate and Insightful Closed-Form Prediction of Subthreshold SRAM Hold Failure Rate

Author:

Van Brandt Leopold1ORCID,Saeidi Roghayeh1,Bol David1ORCID,Flandre Denis1ORCID

Affiliation:

1. ICTEAM Institute, Université Catholique de Louvain, Ottignies-Louvain-la-Neuve, Belgium

Funder

National Fund for Scientific Research (FNRS) of Belgium under FRIA Grant

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering,Hardware and Architecture

Reference38 articles.

1. Dynamic single-p-well SRAM bitcell characterization with back-bias adjustment for optimized wide-voltage-range SRAM operation in 28 nm UTBB FD-SOI;thomas;IEDM Tech Dig,2014

2. Noise margin criteria for digital logic circuits

3. Nanometer Device Scaling in Subthreshold Logic and SRAM

4. Static-noise margin analysis of MOS SRAM cells

5. Interests and Limitations of Technology Scaling for Subthreshold Logic

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