Analog Circuit Yield Optimization via Freeze–Thaw Bayesian Optimization Technique-Reference-Cited by-同舟云学术

Analog Circuit Yield Optimization via Freeze–Thaw Bayesian Optimization Technique

Published:2022-11 Issue:11 Volume:41 Page:4887-4900
ISSN:0278-0070
Container-title:IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
language:
Short-container-title:IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

Author:

Wang Xiaodong¹^ORCID,Yan Changhao¹^ORCID,Ma Yuzhe²^ORCID,Yu Bei³^ORCID,Yang Fan¹^ORCID,Zhou Dian⁴^ORCID,Zeng Xuan¹^ORCID

Affiliation:

1. Microelectronics Department, State Key Laboratory of ASIC & System, Fudan University, Shanghai, China

2. Microelectronics Thrust, The Hong Kong University of Science and Technology (Guangzhou), Guangzhou, China

3. Department of Computer Science and Engineering, The Chinese University of Hong Kong, Hong Kong, SAR, China

4. Department of Electrical Engineering, The University of Texas at Dallas, Richardson, TX, USA

Funder

National Key Research and Development Program of China

National Natural Science Foundation of China (NSFC) Research Projects

Research Grants Council of Hong Kong SAR

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering,Computer Graphics and Computer-Aided Design,Software

Link

http://xplorestaging.ieee.org/ielx7/43/9928799/09706275.pdf?arnumber=9706275

Reference43 articles.

1. Efficient Multiple Starting Point Optimization for Automated Analog Circuit Optimization via Recycling Simulation Data;bo peng;Design Automation Test in Europe Conference Exhibition (DATE),2016

2. Global versus local search in constrained optimization of computer models;schonlau;Lecture Notes-Monograph Series,1998

3. An Efficient Bayesian Optimization Approach for Automated Optimization of Analog Circuits

4. GCN-RL Circuit Designer: Transferable Transistor Sizing with Graph Neural Networks and Reinforcement Learning

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