A Statistical Gate Sizing Method for Timing Yield and Lifetime Reliability Optimization of Integrated Circuits-Reference-Cited by-同舟云学术

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A Statistical Gate Sizing Method for Timing Yield and Lifetime Reliability Optimization of Integrated Circuits

Published:2021-04-01 Issue:2 Volume:9 Page:759-773
ISSN:2168-6750
Container-title:IEEE Transactions on Emerging Topics in Computing
language:
Short-container-title:IEEE Trans. Emerg. Topics Comput.

Author:

Ebrahimipour S. M.,Ghavami Behnam^ORCID,Raji Mohsen^ORCID

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Computer Science Applications,Human-Computer Interaction,Information Systems,Computer Science (miscellaneous)

Link

http://xplorestaging.ieee.org/ielx7/6245516/9447283/09069424.pdf?arnumber=9069424

Cited by 11 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. GNN-Based INC and IVC Co-Optimization for Aging Mitigation;2024 IEEE European Test Symposium (ETS);2024-05-20

2. DNN-Based Optimization to Significantly Speed Up and Increase the Accuracy of Electronic Circuit Design;IEEE Transactions on Circuits and Systems I: Regular Papers;2024-03

3. Yield Maximization of Flip-Flop Circuits Based on Deep Neural Network and Polyhedral Estimation of Nonlinear Constraints;IEEE Access;2024

4. Path-Based Delay Variation Models for Parallel-Prefix Adders;IEEE Transactions on Emerging Topics in Computing;2023-07-01

5. Joint Timing Yield and Lifetime Reliability Optimization of Integrated Circuits;Lifetime Reliability-aware Design of Integrated Circuits;2022-11-17

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