Performance Investigation of Source Extension Approach on III–V Vertical Tunnel FET-Reference-Cited by-同舟云学术

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Performance Investigation of Source Extension Approach on III–V Vertical Tunnel FET

Published:2024 Issue: Volume:12 Page:56439-56447
ISSN:2169-3536
Container-title:IEEE Access
language:
Short-container-title:IEEE Access

Author:

Saravanan M.¹,Parthasarathy Eswaran²^ORCID

Affiliation:

1. Department of Electronics and Communication Engineering, Sri Eshwar College of Engineering, Coimbatore, Tamil Nadu, India

2. Department of Electronics and Communication Engineering, SRM Institute of Science and Technology, Kattankulathur, Chennai, India

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Link

http://xplorestaging.ieee.org/ielx7/6287639/10380310/10504816.pdf?arnumber=10504816

Reference25 articles.

1. A review of III-V Tunnel Field Effect Transistors for future ultra low power digital/analog applications

2. Negative drain-induced barrier lowering and negative differential resistance effects in negative-capacitance transistors

3. Analysis on electrical parameters including temperature and interface trap charges in gate overlap Ge source step shape double gate TFET

4. Analytical drain current model development of twin gate TFET in subthreshold and super threshold regions

5. Design and Performance Optimization of Dopingless Vertical Nanowire TFET Using Gate Stacking Technique

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