Design and Performance Optimization of Dopingless Vertical Nanowire TFET Using Gate Stacking Technique-Reference-Cited by-同舟云学术

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Design and Performance Optimization of Dopingless Vertical Nanowire TFET Using Gate Stacking Technique

Published:2022-05-10 Issue:7 Volume:51 Page:4005-4013
ISSN:0361-5235
Container-title:Journal of Electronic Materials
language:en
Short-container-title:J. Electron. Mater.

Author:

Bhardwaj Anjana^ORCID,Kumar Pradeep,Raj Balwinder,Anand Sunny

Publisher

Springer Science and Business Media LLC

Subject

Materials Chemistry,Electrical and Electronic Engineering,Condensed Matter Physics,Electronic, Optical and Magnetic Materials

Link

https://link.springer.com/content/pdf/10.1007/s11664-022-09658-9.pdf

Reference25 articles.

1. A.K. Singh, M.R. Tripathy, K. Baral, P.K. Singh, and S. Jit, Impact of interface trap charges on device level performances of a lateral/vertical gate stacked Ge/Si TFET-on-SELBOX-substrate. Appl. Phys. A 126, 1 (2020).

2. B. Cheng, M. Cao, R. Rao, A. Inani, P.V. Voorde, W.M. Greene, J.M. Stork, Z. Yu, P.M. Zeitzoff, and J.C. Woo, The impact of high-/spl kappa/gate dielectrics and metal gate electrodes on sub-100 nm MOSFETs. IEEE Trans. Electron Devices 46, 1537 (1999).

3. S. Agarwal, G. Klimeck, and M. Luisier, Leakage-reduction design concepts for low-power vertical tunneling field-effect transistors. IEEE Electron Device Lett. 31, 621 (2010).

4. M.J. Kumar, and S. Janardhanan, Doping-less tunnel field effect transistor: Design and investigation. IEEE Trans. Electron Devices 60, 3285 (2013).

5. M.R. Tripathy, A. Samad, A.K. Singh, P.K. Singh, K. Baral, A.K. Mishra, and S. Jit, Impact of interface trap charges on electrical performance characteristics of a source pocket engineered Ge/Si heterojunction vertical TFET with HfO2/Al2O3 laterally stacked gate oxide. Microelectron. Reliab. 119, 114073 (2021).

Cited by 3 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Design and optimization of vertical nanowire tunnel FET with electrostatic doping;Engineering Research Express;2023-10-19

2. Impact of Pocket Layer on Linearity and Analog/RF Performance of InAs-GaSb Vertical Tunnel Field-Effect Transistor;Journal of Electronic Materials;2023-01-31

3. Vertical-Architecture based Nanowire TFET using Gate Engineering Technique- Design and Analysis;2022 IEEE International Conference on Current Development in Engineering and Technology (CCET);2022-12-23

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