Transient Error Correction Coding Scheme for Reliable Low Power Data Link Layer in NoC-Reference-Cited by-同舟云学术

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Transient Error Correction Coding Scheme for Reliable Low Power Data Link Layer in NoC

Published:2020 Issue: Volume:8 Page:174614-174628
ISSN:2169-3536
Container-title:IEEE Access
language:
Short-container-title:IEEE Access

Author:

Vinodhini M.^ORCID,Murty N. S.^ORCID,Ramesh T. K.

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

General Engineering,General Materials Science,General Computer Science

Link

http://xplorestaging.ieee.org/ielx7/6287639/8948470/09203819.pdf?arnumber=9203819

Cited by 10 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Load balancing-oriented fault-tolerant NoC design;2024 IEEE International Test Conference in Asia (ITC-Asia);2024-08-18

2. A novel technique for flit traversal in network-on-chip router;Computing;2023-07-21

3. An Efficient Single and Double Error Correcting Block Codes with Low Redundancy for Digital Communications;2023 International Conference on Advancement in Computation & Computer Technologies (InCACCT);2023-05-05

4. A Top-Down Modeling Approach for Networks-on-Chip Components Design: A Switch as Case Study;IEEE Access;2023

5. Impact of Maximum Hops Per Cycle On Network-on-Chip Router using Express Bypass Channels;2022 IEEE 4th PhD Colloquium on Emerging Domain Innovation and Technology for Society (PhD EDITS);2022-11-04

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