A Top-Down Modeling Approach for Networks-on-Chip Components Design: A Switch as Case Study
Author:
Affiliation:
1. Department of Electrical Engineering, CINVESTAV, Zapopan, México
2. Centro de Investigación, Innovación y Desarrollo en Telecomunicaciones (CIDTE), Universidad Autónoma de Zacatecas, Zacatecas, México
Funder
Consejo Nacional de Ciencia y Tecnología
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
Subject
General Engineering,General Materials Science,General Computer Science,Electrical and Electronic Engineering
Link
http://xplorestaging.ieee.org/ielx7/6287639/10005208/10011223.pdf?arnumber=10011223
Reference91 articles.
1. Automatic Tool for Fast Generation of Custom Convolutional Neural Networks Accelerators for FPGA
2. Bufferless Network-on-Chips With Bridged Multiple Subnetworks for Deflection Reduction and Energy Savings
3. CHIPPER: A low-complexity bufferless deflection router
4. An Approximate Bufferless Network-on-Chip
5. Design of an accelerator-rich architecture by integrating multiple heterogeneous coarse grain reconfigurable arrays over a network-on-chip
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