Design of an accelerator-rich architecture by integrating multiple heterogeneous coarse grain reconfigurable arrays over a network-on-chip-Reference-Cited by-同舟云学术

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Design of an accelerator-rich architecture by integrating multiple heterogeneous coarse grain reconfigurable arrays over a network-on-chip

Published:2014-06 Issue: Volume: Page:
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Container-title:2014 IEEE 25th International Conference on Application-Specific Systems, Architectures and Processors
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Author:

Hussain Waqar,Airoldi Roberto,Hoffmann Henry,Ahonen Tapani,Nurmi Jari

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/6857731/6868606/06868647.pdf?arnumber=6868647

Cited by 10 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. A Top-Down Modeling Approach for Networks-on-Chip Components Design: A Switch as Case Study;IEEE Access;2023

2. Intelligent Cognitive Radio Architecture Applying Machine Learning and Reconfigurability;2021 IEEE Nordic Circuits and Systems Conference (NorCAS);2021-10-26

3. Aceleradores Reconfiguráveis no Projeto Multicore: uma análise de custo versus benefício;HOLOS;2020-12-16

4. A framework to generate domain-specific manycore architectures from dataflow programs;Microprocessors and Microsystems;2020-02

5. Generating Optimized Multicore Accelerator Architectures;2019 IX Brazilian Symposium on Computing Systems Engineering (SBESC);2019-11

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