Impact of Maximum Hops Per Cycle On Network-on-Chip Router using Express Bypass Channels-Reference-Cited by-同舟云学术

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Impact of Maximum Hops Per Cycle On Network-on-Chip Router using Express Bypass Channels

Published:2022-11-04 Issue: Volume: Page:
ISSN:
Container-title:2022 IEEE 4th PhD Colloquium on Emerging Domain Innovation and Technology for Society (PhD EDITS)
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Author:

Katta Monika¹,Ramesh T. K.¹,Plosila Juha²

Affiliation:

1. Amrita School of Engineering,Amrita Vishwa Vidyapeetham,Department of Electronics & Communication Engineering,Bengaluru,India

2. University of Turku,Autonomous Systems Laboratory, Faculty of Science and Engineering,Department of Future Technologies,Finland

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/9955040/9955251/09955262.pdf?arnumber=9955262

Reference5 articles.

1. Latency Improvement by Using Fill VC Allocation for Network on Chip

2. Smart: Single-Cycle Multihop Traversals over a Shared Network on Chip

3. Transient Error Correction Coding Scheme for Reliable Low Power Data Link Layer in NoC

4. Breaking the on-chip latency barrier using SMART

5. SB-Router: A Swapped Buffer Activated Low Latency Network-on-Chip Router

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