Breaking the on-chip latency barrier using SMART-Reference-Cited by-同舟云学术

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Breaking the on-chip latency barrier using SMART

Published:2013-02 Issue: Volume: Page:
ISSN:
Container-title:2013 IEEE 19th International Symposium on High Performance Computer Architecture (HPCA)
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Author:

Krishna T.,Chen Chia-Hsin Owen,Woo Cheol Kwon ,Li-Shiuan Peh

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/6518038/6522298/06522334.pdf?arnumber=6522334

Cited by 72 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Traffic-oriented reconfigurable NoC with augmented inter-port buffer sharing;Frontiers of Information Technology & Electronic Engineering;2024-08-16

2. NOVA: NoC-based Vector Unit for Mapping Attention Layers on a CNN Accelerator;2024 Design, Automation & Test in Europe Conference & Exhibition (DATE);2024-03-25

3. Applying SMART-Based Power Gating Approach in NoC System;Journal of Circuits, Systems and Computers;2024-01-03

4. DAG-Order: An Order-Based Dynamic DAG Scheduling for Real-Time Networks-on-Chip;ACM Transactions on Architecture and Code Optimization;2023-12-15

5. A novel technique for flit traversal in network-on-chip router;Computing;2023-07-21

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