Distributed Cycling in Charge Trap-Based 3D NAND Arrays: Model and Qualification Tests Implications
Author:
Affiliation:
1. NAND Technology Development, Micron Technology, Inc. Boise,ID,USA,83716
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/10145914/10145815/10145969.pdf?arnumber=10145969
Reference15 articles.
1. Flash EEPROM Threshold Instabilities due to Charge Trapping During Program/Erase Cycling
2. A step ahead toward a new microscopic picture for charge trapping/detrapping in flash memories
3. Impact of Cycling Induced Intercell Trapped Charge on Retention Charge Loss in 3-D NAND Flash Memory
4. Investigation of the threshold voltage instability after distributed cycling in nanoscale NAND Flash memory arrays
5. Cycling-Induced Charge Trapping/Detrapping in Flash Memories—Part II: Modeling
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