A 4.7-ps Resolution Recirculating Cyclic Vernier TDC Using DWA-Based Mismatch Correction and a Register-Based Time Amplifier-Reference-Cited by-同舟云学术

A 4.7-ps Resolution Recirculating Cyclic Vernier TDC Using DWA-Based Mismatch Correction and a Register-Based Time Amplifier

Published:2023 Issue: Volume:72 Page:1-13
ISSN:0018-9456
Container-title:IEEE Transactions on Instrumentation and Measurement
language:
Short-container-title:IEEE Trans. Instrum. Meas.

Author:

Nguyen Van-Nhan¹^ORCID,Lee Jong-Wook¹^ORCID

Affiliation:

1. Department of Electronics and Information Convergence Engineering, Information and Communication System-on-chip (SoC) Research Center, Kyung Hee University, Yongin, Republic of Korea

Funder

National Research Foundation of Korea through the Basic Science Research Program

National Research Foundation of Korea funded by the Ministry of Science and ICT through the National Research and Development Program

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering,Instrumentation

Link

http://xplorestaging.ieee.org/ielx7/19/10012124/10026809.pdf?arnumber=10026809

Reference34 articles.

1. A 4-GS/s 11.3-mW 7-bit Time-Based ADC With Folding Voltage-to-Time Converter and Pipelined TDC in 65-nm CMOS

2. A 9 bit, 1.12 ps Resolution 2.5 b/Stage Pipelined Time-to-Digital Converter in 65 nm CMOS Using Time-Register

3. High-speed analogue–digital convertor

4. Enhancing Nutt-Based Time-to-Digital Converter Performance With Internal Systematic Averaging

Cited by 2 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. A Novel FPGA-Based Delay-Line Implementation and Interpolation Method Using TDCs;2023 International Conference on Sensing, Measurement & Data Analytics in the era of Artificial Intelligence (ICSMD);2023-11-02

2. A Novel 550-fs Time-Resolution 7.5-bit Stochastic Time-to-Digital Converter Based on Two Arbiter Groups;IEEE Transactions on Instrumentation and Measurement;2023