A Novel 550-fs Time-Resolution 7.5-bit Stochastic Time-to-Digital Converter Based on Two Arbiter Groups
Author:
Affiliation:
1. Institute of Electronic Computer-Aided Design and the Key Laboratory of High-Speed Circuit Design and Electromagnetic Compatibility, Ministry of Education, Xidian University, Xi’an, China
Funder
National Natural Science Foundation of China
Natural Science Basic Research Program of Shaanxi
Fundamental Research Funds for the Central Universities of China
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
Subject
Electrical and Electronic Engineering,Instrumentation
Link
http://xplorestaging.ieee.org/ielx7/19/10012124/10143272.pdf?arnumber=10143272
Reference36 articles.
1. 1.3 V 20 ps time-to-digital converter for frequency synthesis in 90-nm CMOS
2. A Multiphase-Output Delay-Locked Loop With a Novel Start-Controlled Phase/Frequency Detector
3. A 529-μW Fractional-N All-Digital PLL Using TDC Gain Auto-Calibration and an Inverse-Class-F DCO in 65-nm CMOS
4. A low-jitter and fractional-resolution injection-locked clock multiplier using a DLL-based real-time PVT calibrator with replica-delay cells;kim;IEEE J Solid-State Circuits,2016
5. A Reconfigurable Vernier Time-to-Digital Converter With 2-D Spiral Comparator Array and Second-Order $\Delta \Sigma$ Linearization
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