A 9 bit, 1.12 ps Resolution 2.5 b/Stage Pipelined Time-to-Digital Converter in 65 nm CMOS Using Time-Register-Reference-Cited by-同舟云学术

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A 9 bit, 1.12 ps Resolution 2.5 b/Stage Pipelined Time-to-Digital Converter in 65 nm CMOS Using Time-Register

Published:2014-04 Issue:4 Volume:49 Page:1007-1016
ISSN:0018-9200
Container-title:IEEE Journal of Solid-State Circuits
language:
Short-container-title:IEEE J. Solid-State Circuits

Author:

Kim KwangSeok,Yu WonSik,Cho SeongHwan

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering

Link

http://xplorestaging.ieee.org/ielx7/4/6777594/06712925.pdf?arnumber=6712925

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1. A 0.013 mm² 3.2-ns Input Range 10-Bit Cyclic Time-to-Digital Converter Using Gated Ring Oscillator With Phase Domain Reset in 65-nm CMOS;IEEE Transactions on Circuits and Systems II: Express Briefs;2024-08

2. High-Accuracy Phase Frequency Detection Technology Based on BDS Time and Frequency Signals;Sensors;2024-07-16

3. All-Digital Time Register Based On Recursive Delay-Line;2024 Panhellenic Conference on Electronics & Telecommunications (PACET);2024-03-28

4. Moving Average Filter in Time-Mode Signal Processing;2024 Panhellenic Conference on Electronics & Telecommunications (PACET);2024-03-28

5. A 12-bit, 27.8-ps resolution, Anti-PVT variation multi-parallel sampling based coarse-fine TDC for LiDAR sensors;Microelectronics Journal;2024-01

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