Setup and Hold Time Analysis of D Flip-Flop based on CMOS and GNRFET-Reference-Cited by-同舟云学术

Setup and Hold Time Analysis of D Flip-Flop based on CMOS and GNRFET

Published:2023-02-10 Issue: Volume: Page:
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Container-title:2023 IEEE 3rd International Conference on Technology, Engineering, Management for Societal impact using Marketing, Entrepreneurship and Talent (TEMSMET)
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Author:

Jayashree L¹,Suveditta B¹,Vasundhara Patel K.S¹

Affiliation:

1. BMS College of Engineering,Dept. of Electronics and CommunicationEngineering,Bengaluru,India

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/10149893/10149894/10150117.pdf?arnumber=10150117

Reference10 articles.

1. High speed and low power preset-able modified TSPC D flip-flop design and performance comparison with TSPC D flip-flop

2. Low Power AVLS-TSPC based 2/3 Pre-Scaler;anirvinnan;International journal of engineering and advanced technology(IJEAT),2019

3. Comparative Analysis of basic Sequential Circuits based on CMOS and Graphene Nano Ribbon Transistors;ravishamsantha;in Grenze International Journal of Engineering and Technology June Issue,0

4. Performance optimization of GNRFET Inverter at 32nm technology node

5. Design and Comparative Analysis of D-Flip-Flop using conditional pass Transistor logic for High-Performance with Low-Power Systems;murugasami associate professor;Microprocessors and Microsystems,2019

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