Enhancing Static Timing Analysis Efficiency for RISC-V Processors Through Optimization Techniques
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Publisher
Springer Nature Singapore
Link
https://link.springer.com/content/pdf/10.1007/978-981-97-4700-9_37
Reference10 articles.
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2. Chen, Y., Dong, X., Shih, W.-K., Zhuo, C.: Invited paper: unleashing the potential of machine learning: harnessing the dynamics of supply noise for timing sign-off. In: 2023 IEEE/ACM International Conference on Computer Aided Design (ICCAD), San Francisco, CA, USA, pp. 1–6 (2023). https://doi.org/10.1109/ICCAD57390.2023.10324001
3. Shah, A., Nayyar, R., Sinha, A.: Silicon-proven timing signoff methodology using hazard-free robust path delay tests. IEEE Des. Test 37(4), 7–13 (2020). https://doi.org/10.1109/MDAT.2020.2968253
4. Wei, K.: Exploring the optimized AI SoC design flow. In: 2023 International VLSI Symposium on Technology, Systems and Applications (VLSI-TSA/VLSI-DAT), HsinChu, Taiwan, pp. 1–1 (2023). https://doi.org/10.1109/VLSI-TSA/VLSI-DAT57221.2023.10133942
5. Jayashree, L., Suveditta, B., Vasundhara Patel, K.S.: Setup and hold time analysis of D flip-flop based on CMOS and GNRFET. In: 2023 IEEE 3rd International Conference on Technology, Engineering, Management for Societal impact using Marketing, Entrepreneurship and Talent (TEMSMET), Mysuru, India, pp. 1–5 (2023). https://doi.org/10.1109/TEMSMET56707.2023.10150117
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