1. Clocked CMOS calculator circuitry;Suzuki;IEEE J. Solid-State Circuits,1973
2. Design perspective of low power, high efficiency shift registers;Marufuzzaman;J. Theor. Appl. Inf. Technol.,2015
3. Low-power clock distribution using a current-pulsed clocked Flip-flop;Islam;IEEE Trans. Circuits Syst I,2015
4. Level-converting retention Flip-flop for reducing standby power in ZigBee SoCs;Park;IEEE Trans. Very Large Scale Integr. VLSI Syst.,2015
5. D. Gluzer and S. Wimer, “Probability-driven multi bit Flip-flop design optimization”, Available at http://www.eng.biu.ac.il/segalla/computer-engineering-tech-reports/, pp. 1–16, Feb. 2015.