Thermal Modeling and Analysis of High Bandwidth Memory in 2.5D Si-interposer Systems

Author:

Kim Taehwan1,Lee Jonggyu1,Kim Jaechoon1,Lee Eung-Chang2,Hwang Heejung1,Kim Youngdeuk1,Oh Dan Kyung Suk1

Affiliation:

1. Package Design Team, Samsung Electronics Co., Ltd.,Hwaseong-si,South Korea

2. DRAM Memory Planning, Samsung Electronics Co., Ltd.,Hwaseong-si,South Korea

Publisher

IEEE

Reference8 articles.

Cited by 5 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献

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2. FEA Simulations for Thermal Distributions of Large Scale 3DIC Packages;IEEE Access;2024

3. Electrical and Thermal Analysis of Bumpless Build Cube 3D Using Wafer-on-Wafer and Chip-on-Wafer for Near Memory Computing;2023 IEEE 73rd Electronic Components and Technology Conference (ECTC);2023-05

4. Thermal Improvement of HBM with Joint Thermal Resistance Reduction for Scaling 12 Stacks and Beyond;2023 IEEE 73rd Electronic Components and Technology Conference (ECTC);2023-05

5. Reliability Characterization of HBM featuring $\text{HK}+\text{MG}$ Logic Chip with Multi-stacked DRAMs;2023 IEEE International Reliability Physics Symposium (IRPS);2023-03

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