Simulation Modeling of 600mm X600mm Fan-Out Panel Level for Warpage Behavior Based on Chip First
Author:
Affiliation:
1. ASE Technology - 26,Kaohsiung City 811,Taiwan
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/10348606/10348630/10348732.pdf?arnumber=10348732
Reference11 articles.
1. Comparison of Mechanical Modeling to Warpage Estimation of RDL-First Fan-Out Panel-Level Packaging
2. Panel Warpage of Fan-Out Panel-Level Packaging Using RDL-First Technology
3. Warpage Analysis and Optimization of Fan-Out Panel-Level Packaging with Chip-Last Process
4. Warpage Analysis with Newly Molding Material of Fan-Out Panel Level Packaging and the Board Level Reliability Test Results
5. Studying Asymmetric Warpage Behavior of Panel-Level Packages Using Process Modeling Techniques and Viscoelasticity Theory
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1. Problems of Microsystems Reliability Design with Redistribution Layers in Wafer Level Packaging;2024 IEEE 25th International Conference of Young Professionals in Electron Devices and Materials (EDM);2024-06-28
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