Problems of Microsystems Reliability Design with Redistribution Layers in Wafer Level Packaging
Author:
Affiliation:
1. Institute of Nano and Microsystem Technology National Research University of Electronic Technology,Moscow,Russia
Funder
Ministry of Education and Science
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx8/10614947/10614948/10615019.pdf?arnumber=10615019
Reference12 articles.
1. Warpage Analysis and Optimization of Fan-Out Panel-Level Packaging with Chip-Last Process
2. Advanced Fanout Packaging Technology for Hybrid Substrate Integration
3. A Transformer using two RDL metal layers based on Fan-Out Panel Level Package Technology
4. Study of the Influence of Mechanical and Temperature Effects on the Level of Stresses and Deformations in 3D Microassemblies Hermetically Sealed with Two Types of Compounds
5. Simulation Modeling of 600mm X600mm Fan-Out Panel Level for Warpage Behavior Based on Chip First
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