A Graph-Based 3D IC Partitioning Technique
Author:
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/6901614/6903314/06903432.pdf?arnumber=6903432
Cited by 9 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献
1. A Cost-Driven Chip Partitioning Method for Heterogeneous 3D Integration;ACM Transactions on Design Automation of Electronic Systems;2024-07-09
2. Genetic Algorithm Based 3D IC Partitioning Approach for TSV Minimization and Efficient Layer Assignment;IETE Journal of Research;2024-01-02
3. An efficient 3D IC partitioning approach using satin bowerbird optimization for reduced TSV count and improved heat dissipation;Engineering Research Express;2023-11-14
4. 3D IC Partitioning Approach for Achieving Lower TSV Count and Reduced Heat Dissipation using Particle Swarm Optimization;2022 First International Conference on Electrical, Electronics, Information and Communication Technologies (ICEEICT);2022-02-16
5. An efficient partitioning and placement based fault TSV detection in 3D-IC using deep learning approach;Journal of Ambient Intelligence and Humanized Computing;2021-03-05
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