Genetic Algorithm Based 3D IC Partitioning Approach for TSV Minimization and Efficient Layer Assignment
Author:
Affiliation:
1. Department of Computer Science, Sonarpur Mahavidyalaya, Sonarpur, West Bengal, India
2. Department of Computer Science, Ramakrishna Mission Residential College (Autonomous), Narendrapur, West Bengal, India
Publisher
Informa UK Limited
Subject
Electrical and Electronic Engineering,Computer Science Applications,Theoretical Computer Science
Link
https://www.tandfonline.com/doi/pdf/10.1080/03772063.2023.2298500
Reference33 articles.
1. Intel Microprocessor Quick Reference Guide December 2012 https://www.intel.com/pressroom/kits/quickreffam.htm#xeonll
2. B. Hoefflinger, ITRS: The international technology roadmap for semiconductors, in: B. Hoefflinger (Ed.), Chips 2020, The frontiers collection, Springer, Berlin, Heidelberg, 2012, pp. 161–74.
3. Design partitioning and layer assignment for 3D integrated circuits using Tabu search and simulated annealing;Sait S. M.;J. Appl Res Technol.,2016
4. Three-Dimensional Integrated Circuit (3D IC) Key Technology: Through-Silicon Via (TSV)
5. 3D‐IC partitioning method based on genetic algorithm
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