Comparative performance analysis of FinFET, CNTFET and GNRFET for low power digital logic circuit applications
Author:
Affiliation:
1. Lovely Professional University,VLSI Design, School of Electronics and Electrical Engineering,Phagwara,Punjab,India
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/10032824/10032825/10032958.pdf?arnumber=10032958
Reference25 articles.
1. Design of CMOS ternary logic family based on single supply voltage
2. An optimal gate design for the synthesis of ternary logic circuits
3. Design of ternary logic circuits using CNTFET
4. Enabling energy-efficient ternary logic gates using CNFETs
5. Full-Swing Local Bitline SRAM Architecture Based on the 22-nm FinFET Technology for Low-Voltage Operation
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2. An Efficient Approach to Design Ternary Logic Circuits with GNRFETs;2024 IEEE International Conference on Information Technology, Electronics and Intelligent Communication Systems (ICITEICS);2024-06-28
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4. Design of a Low Power Complementary Current Controlled Skewed Delay Voltage Controlled Oscillator using CNTFET;2023 International Conference on Artificial Intelligence and Applications (ICAIA) Alliance Technology Conference (ATCON-1);2023-04-21
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