Design of CMOS ternary logic family based on single supply voltage-Reference-Cited by-同舟云学术

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Design of CMOS ternary logic family based on single supply voltage

Published:2015-01 Issue: Volume: Page:
ISSN:
Container-title:2015 International Conference on Pervasive Computing (ICPC)
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Author:

Gaikwad V. T.,Deshmukh P. R.

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/7063888/7086957/07087114.pdf?arnumber=7087114

Cited by 10 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Speed-Area-Power Efficient Ternary Logic Gate Implementation Based on Typical MOS Transistors;2024 International Conference on Electronics, Information, and Communication (ICEIC);2024-01-28

2. Design of Encoder based Half-Adder using GNRFET Technology in Ternary Logic;2023 International Conference on Next Generation Electronics (NEleX);2023-12-14

3. High-performance ternary designs using graphene nanoribbon transistors;Materials Today: Proceedings;2023-07

4. Noise Margin analysis of Efficient CNTFET- based Standard Ternary Inverter;2023 International Conference for Advancement in Technology (ICONAT);2023-01-24

5. Comparative performance analysis of FinFET, CNTFET and GNRFET for low power digital logic circuit applications;2022 IEEE International Conference of Electron Devices Society Kolkata Chapter (EDKCON);2022-11-26

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