High-performance ternary designs using graphene nanoribbon transistors

Author:

Obulesu Battari,Dwaraka Praveena Hirald,Javid Basha Shaik,Sruthi M.V.,Sunil Kumar K.,Ashokkumar N.

Publisher

Elsevier BV

Subject

General Medicine

Reference21 articles.

1. Investigation of crosstalk issues for MWCNT bundled TSVs in ternary logic;Basha;ECS J. Solid State Sci. Technol.,2022

2. Crosstalk reduction in copper on-chip interconnects with graphene barrier for ternary logic applications;Madhuri;Int. J. Circuit Theory Appl.,2020

3. High-performance and energy-efficient CNFET-based designs for ternary logic circuits;Jaber;IEEE Access,2019

4. V. T. Gaikwad and P. R. Deshmukh, “Design of CMOS Ternary Logic Family based on Single Supply Voltage,”2015 International Conference on Pervasive Computing (ICPC), pp. 1-6, April 2015.

5. Designing ternary quantum-dot cellular automata logic circuits based upon an alternative model;Mohaghegh;Comput. Electr. Eng.,2018

Cited by 3 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献

1. Design and Simulation of New High Speed, Low Power D-Flip-Flops, Implemented Using Graphene Nanoribbon and Carbon Nanotube Field Effect Transistors;Iranian Journal of Science and Technology, Transactions of Electrical Engineering;2024-06-19

2. Tri-state GNRFET-based fast and energy-efficient ternary multiplier;AEU - International Journal of Electronics and Communications;2024-04

3. High-speed and power-efficient ternary logic designs using GNR transistors;e-Prime - Advances in Electrical Engineering, Electronics and Energy;2024-03

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