Enabling energy-efficient ternary logic gates using CNFETs
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Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/8103843/8117249/08117467.pdf?arnumber=8117467
Cited by 18 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献
1. Design of Ternary and Quaternary Asynchronous Up/Down Counter using CNTFET;AEU - International Journal of Electronics and Communications;2024-05
2. Novel design of power-efficient quaternary logic gates using CNTFET;International Journal of Electronics;2023-05-14
3. Design of CNTFET-Based Ternary and Quaternary Magnitude Comparator;Circuits, Systems, and Signal Processing;2023-05-03
4. A Novel Low-Complexity Power-Efficient Design of Standard Ternary Logic Gates using CNTFET;2023 International Conference on Computer, Electrical & Communication Engineering (ICCECE);2023-01-20
5. Comparative performance analysis of FinFET, CNTFET and GNRFET for low power digital logic circuit applications;2022 IEEE International Conference of Electron Devices Society Kolkata Chapter (EDKCON);2022-11-26
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