Design of CNTFET-Based Ternary and Quaternary Magnitude Comparator
Author:
Publisher
Springer Science and Business Media LLC
Subject
Applied Mathematics,Signal Processing
Link
https://link.springer.com/content/pdf/10.1007/s00034-023-02380-9.pdf
Reference26 articles.
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2. A.K. Dadoria, K. Khare, Design and analysis of low-power adiabatic logic circuits by using CNTFET Technology. Circuits Syst. Signal Process. 38(9), 4338–4356 (2019). https://doi.org/10.1007/s00034-019-01059-4
3. A. Daraei, S.A. Hosseini, Novel energy-efficient and high-noise margin quaternary circuits in nanoelectronics. AEU-Int. J. Electron. C. 105, 145–162 (2019). https://doi.org/10.1016/j.aeue.2019.04.012
4. J. Deng, H.S.P. Wong, A compact SPICE model for carbon-nanotube field-effect transistors including nonidealities and its application—part II: full device model and circuit performance benchmarking. IEEE Trans. Electron Devices. 54(12), 3195–3205 (2007). https://doi.org/10.1109/TED.2007.909043
5. J. Deng, H.S.P. Wong, A compact SPICE model for carbon-nanotube field-effect transistors including nonidealities and its application—part I: model of the intrinsic channel region. IEEE Trans. Electron Devices. 54(12), 3186–3194 (2007). https://doi.org/10.1109/TED.2007.909030
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