An optimal gate design for the synthesis of ternary logic circuits-Reference-Cited by-同舟云学术

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An optimal gate design for the synthesis of ternary logic circuits

Published:2018-01 Issue: Volume: Page:
ISSN:
Container-title:2018 23rd Asia and South Pacific Design Automation Conference (ASP-DAC)
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Author:

Kim Sunmean,Lim Taeho,Kang Seokhyeong

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/8291862/8297256/08297369.pdf?arnumber=8297369

Cited by 36 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

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2. Enhancing high-speed digital systems: MVL circuit design with CNTFET and RRAM;Journal of King Saud University - Computer and Information Sciences;2024-04

3. Low power CNTFET-based ternary multiplier for digital signal processing applications;Engineering Research Express;2024-02-06

4. Low Power-Delay-Product Ternary Adder with Optimized Ternary Cycling Gates;2023 6th World Symposium on Communication Engineering (WSCE);2023-09-27

5. Exploration of Ternary Logic Using T-CMOS for Circuit-Level Design;IEEE Transactions on Circuits and Systems I: Regular Papers;2023-09

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