Low power and high speed 8x8 bit multiplier using non-clocked pass transistor logic-Reference-Cited by-同舟云学术

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Low power and high speed 8x8 bit multiplier using non-clocked pass transistor logic

Published:2007-11 Issue: Volume: Page:
ISSN:
Container-title:2007 International Conference on Intelligent and Advanced Systems
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Author:

Senthilpari C.,Singh Ajay Kumar,Diwakar K.

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx5/4638683/4658336/04658609.pdf?arnumber=4658609

Cited by 8 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Low-Power, High-Speed, and Area-Efficient Multiplier Based on the PTL Logic Style;IEEE Transactions on Circuits and Systems II: Express Briefs;2024-07

2. Low-Power Pass-Transistor Logic-Based Full Adder and 8-Bit Multiplier;Electronics;2023-07-25

3. PPA Based MAC Unit Using Vedic Multiplier and XOR Logic;Communications in Computer and Information Science;2023

4. Analysis and Implementation of Less Delay and Low Area DT Multiplier;Lecture Notes in Networks and Systems;2022

5. Novel CMOS multi-bit counter for speed-power optimization in multiplier design;AEU - International Journal of Electronics and Communications;2018-10

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