PPA Based MAC Unit Using Vedic Multiplier and XOR Logic
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Publisher
Springer Nature Switzerland
Link
https://link.springer.com/content/pdf/10.1007/978-3-031-27622-4_22
Reference15 articles.
1. Dwivedi, K., Sharma, R.K., Chunduri, A.: Hybrid multiplier-based optimized MAC unit. In: 9th International Conference on Computing, Communication and Networking Technologies (ICCCNT) (2018)
2. Krishna Vamsi, A.S., Ramesh, S.R.: An efficient design of 16 bit MAC unit using Vedic mathematics. In: 2019 International Conference on Communication and Signal Processing (ICCSP), Chennai, India, pp. 0319–0322 (2019)
3. Jithin, S., Prabhu, E.: Parallel multiplier – accumulator unit based on vedic mathematics. ARPN J. Eng. Appl. Sci. 10(8), 3608–3613 (2015)
4. Ahish, S., Kumar, Y.B.N., Sharma, D., Vasantha, M.H.: Design of high performance multiply accumulate computation unit. In: IEEE International Advance Computing Conference (IACC), pp. 915–918, June (2015)
5. Yuvraj, M., Bhaskar, N., Kailath, B.J.: Design of optimized MAC unit using integrated Vedic multiplier. In: International Conference on Microelectronic Devices, Circuits and Systems (ICMDCS) (2017)
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