Low-Power, High-Speed, and Area-Efficient Multiplier Based on the PTL Logic Style-Reference-Cited by-同舟云学术

Low-Power, High-Speed, and Area-Efficient Multiplier Based on the PTL Logic Style

Published:2024-07 Issue:7 Volume:71 Page:3538-3542
ISSN:1549-7747
Container-title:IEEE Transactions on Circuits and Systems II: Express Briefs
language:
Short-container-title:IEEE Trans. Circuits Syst. II

Author:

Pan Wanyuan¹^ORCID,Yu Yihe¹^ORCID,Tang Chengcheng¹,Yin Ningyuan²,Yu Zhiyi²^ORCID

Affiliation:

1. School of Microelectronics Science and Technology, Sun Yat-sen University, Zhuhai, China

2. Guangdong Provincial Key Laboratory of Optoelectronic Information Processing Chips and Systems, School of Microelectronics Science and Technology, Sun Yat-sen University, Zhuhai, China

Funder

Key-Area Research and Development Program of Guangdong Province

National Key Research and Development Program of China

National Natural Science Foundation of China

Basic and Applied Basic Research Foundation of Guangdong Province

Zhuhai Industry-Academic Collaboration Program

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Link

http://xplorestaging.ieee.org/ielx7/8920/10581876/10436552.pdf?arnumber=10436552

Reference23 articles.

1. Leakage current: Moore's law meets static power

2. Design of Robust, Energy-Efficient Full Adders for Deep-Submicrometer Design Using Hybrid-CMOS Logic Style

3. Implementation of a high speed multiplier for high-performance and low power applications

4. Low power and high speed 8x8 bit multiplier using non-clocked pass transistor logic

5. A multiplier and squarer generator for high performance DSP applications

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