Author:
Kumar G Ganesh,Sahoo Subhendu K
Cited by
10 articles.
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1. Low-Power, High-Speed, and Area-Efficient Multiplier Based on the PTL Logic Style;IEEE Transactions on Circuits and Systems II: Express Briefs;2024-07
2. Low-Power Pass-Transistor Logic-Based Full Adder and 8-Bit Multiplier;Electronics;2023-07-25
3. Design and Analysis of Low Power MAC for DSP Processor;2023 International Conference on Artificial Intelligence and Applications (ICAIA) Alliance Technology Conference (ATCON-1);2023-04-21
4. Design of Arithmetic Circuits Using an Approximation Computing;2023 9th International Conference on Advanced Computing and Communication Systems (ICACCS);2023-03-17
5. An 8-bit Radix-4 Non-Volatile Parallel Multiplier;Electronics;2021-09-27