Implementation of a high speed multiplier for high-performance and low power applications

Author:

Kumar G Ganesh,Sahoo Subhendu K

Publisher

IEEE

Cited by 9 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献

1. Low-Power Pass-Transistor Logic-Based Full Adder and 8-Bit Multiplier;Electronics;2023-07-25

2. Design and Analysis of Low Power MAC for DSP Processor;2023 International Conference on Artificial Intelligence and Applications (ICAIA) Alliance Technology Conference (ATCON-1);2023-04-21

3. Design of Arithmetic Circuits Using an Approximation Computing;2023 9th International Conference on Advanced Computing and Communication Systems (ICACCS);2023-03-17

4. An 8-bit Radix-4 Non-Volatile Parallel Multiplier;Electronics;2021-09-27

5. RIME;Proceedings of the 26th Asia and South Pacific Design Automation Conference;2021-01-18

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