In-Memory Computing for Machine Learning and Deep Learning
Author:
Affiliation:
1. Dipartimento di Elettronica, Informazione e Bioingegneria, Politecnico di Milano and IU.NET, Milan, Italy
Funder
EU’s Horizon Europe Research and Innovation Programme
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
Subject
Electrical and Electronic Engineering,Electronic, Optical and Magnetic Materials,Biotechnology
Link
http://xplorestaging.ieee.org/ielx7/6245494/10049274/10103697.pdf?arnumber=10103697
Reference189 articles.
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2. Systematic optimization of 1 Gbit perpendicular magnetic tunnel junction arrays for 28 nm embedded STT-MRAM and beyond
3. CMOS-embedded STT-MRAM arrays in 2x nm nodes for GP-MCU applications;shum;Proc Symp VLSI Technol,2017
4. Highly functional and reliable 8Mb STT-MRAM embedded in 28nm logic
5. Highly productive PCRAM technology platform and full chip operation: Based on 4F2(84nm pitch) cell scheme for 1 Gb and beyond
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