The Effect of Deep JFET and P-Well Implant of 1.2kV 4H-SiC MOSFETs
Author:
Affiliation:
1. College of Nanoscale Science and Engineering, State University of New York Polytechnic Institute, Albany, NY, USA
Funder
Office of Energy Efficiency and Renewable Energy (EERE), U.S. Department of Energy, the Vehicle Technologies Program Office
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
Subject
Electrical and Electronic Engineering,Electronic, Optical and Magnetic Materials,Biotechnology
Link
https://ieeexplore.ieee.org/ielam/6245494/9714452/9935108-aam.pdf
Reference14 articles.
1. Non-Isothermal Simulations to Optimize SiC MOSFETs for Enhanced Short-Circuit Ruggedness
2. Area-Efficient, 600V 4H-SiC JBS Diode-Integrated MOSFETs (JBSFETs) for Power Converter Applications
3. Improved Short-Circuit Ruggedness for 1.2kV 4H-SiC MOSFET Using a Deep P-Well Implemented by Channeling Implantation
4. Electrical characterization of 1.2kV SiC MOSFET at extremely high junction temperature
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