SRAM Memory Built in Self-Test using MARCH Algorithm

Author:

Kruthika J.1,Nisha G. R.2,Gayathri R.1,Jeyalakshmi V.3

Affiliation:

1. Sri Venkateshwara College of Engineering,Department of ECE,Sriperumbuthur,India

2. VSSC/ISRO,Trivandrum,India

3. Anna University,Department of ECE,Chennai,India

Publisher

IEEE

Reference17 articles.

1. A review paper on memory fault models and test algorithms

2. BIST Memory Design and Testing;divya;International Journal of Scientific Development and Research,2018

3. Memory Testing and Repairing Using MBIST with Complete Programmability

4. Implementation of March Algorithm based MBIST Architecture for SRAM;radha rani;International Journal of Advanced Research in Computer Engineering & Technology,2012

5. Modified March C-With Concurrency in Testing for Embedded Memory Applications

Cited by 2 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献

1. Novel March WY Approach for Dynamic Fault Detection in Memory BIST;2023 IEEE 16th International Symposium on Embedded Multicore/Many-core Systems-on-Chip (MCSoC);2023-12-18

2. A Dedicated Memory Testing Processor Design;2023 IEEE 16th International Conference on Electronic Measurement & Instruments (ICEMI);2023-08-09

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